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L6911C
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION
s s s
s s
s s s s s s s
OPERATING SUPPLY IC VOLTAGE FROM 5V TO 12V BUSES UP TO 1.3A GATE CURRENT CAPABILITY TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT COMPLIANT WITH VRM 8.4 : 1.3V TO 2.05V WITH 0.05V BINARY STEPS 2.1V TO 3.5V WITH 0.1V BINARY STEPS VOLTAGE MODE PWM CONTROL EXCELLENT OUTPUT ACCURACY: 1% OVER LINE AND TEMPERATURE VARIATIONS VERY FAST LOAD TRANSIENT RESPONSE: FROM 0% TO 100% DUTY CYCLE POWER GOOD OUTPUT VOLTAGE OVERVOLTAGE PROTECTION AND MONITOR OVERCURRENT PROTECTION REALIZED USING THE UPPER MOSFET'S RdsON 200KHz INTERNAL OSCILLATOR OSCILLATOR EXTERNALLY ADJUSTABLE FROM 50KHz TO 1MHz SOFT START AND INHIBIT FUNCTIONS
SO-20 ORDERING NUMBERS: L6911C L6911CTR (Tape and Reel)
APPLICATIONS s POWER SUPPLY FOR ADVANCED MICROPROCESSOR CORE s DISTRIBUTED POWER SUPPLY s HIGH POWER DC-DC REGULATORS
DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 1.30V to 2.05V with 50mV binary steps and from 2.10V to 3.50V with 100mV binary steps. The high precision internal reference assures the selected output voltage to be within 1%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load overcurrent and load overvoltage. An external SCR is triggered to crowbar the input supply in case of hard over-voltage. An internal crowbar is also provided turning on the low side mosfet as long as the overvoltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode.
BLOCK DIAGRAM
Vcc 5 to 12V Vin 5V to12V
PGOOD SS
VCC
OCSET BOOT
MONITOR and PROTECTION OVP RT
UGATE
OSC
PHASE LGATE PGND
Vo 1.300V to 3.500V
VD0 VD1 VD2 VD3 VD4 D/A + E/A + PWM
GND VSEN VFB
D01IN1260
COMP
November 2001
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L6911C
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VBOOT-VPHASE VHGATE-VPHASE OCSET, LGATE, PHASE RT, SS, FB, PGOOD, VSEN, VID0-4 OVP, COMP VCC to GND, PGND Boot Voltage Parameter Value 15 15 15 -0.3 to Vcc+0.3 7 6.5 Unit V V V V V V
THERMAL DATA
Symbol Rth j-amb Tj Tstg TJ Parameter Thermal Resistance Junction to Ambient Maximum junction temperature Storage temperature range Junction temperature range Value 110 150 -40 to 150 0 to 125 Unit C/W C C C
PIN CONNECTION (Top view)
VSEN OCSET SS/INH VID0 VID1 VID2 VID3 VID4 COMP FB
1 2 3 4 5 6 7 8 9 10
D98IN958
20 19 18 17 16 15 14 13 12 11
RT OVP VCC LGATE PGND BOOT UGATE PHASE PGOOD GND
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PIN FUNCTION
Pin Num. 1 2 Name VSEN OCSET Description Connected to the output voltage is able to manage over-voltage conditions and the PGOOD signal. A resistor connected from this pin and the upper Mos Drain sets the current limit protection. The internal 200A current generator sinks a current from the drain through the external resistor. The Over-Current threshold is due to the following equation: I OCSE T R O CS ET IP = --------------------------------------------R DS on The soft start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces through the capacitor 10A. This pin can be used to disable the device forcing a voltage lower than 0.4V Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They are used to program the output voltage as specified in Table 1 and to set the overvoltage and power good thresholds. Connect to GND to program a `0' while leave floating to program a `1'. This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds. If not used may be left floating. This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit High side gate driver output. Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot). Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device This pin is the lower mosfet gate driver output Device supply voltage. The operative nominal supply voltage ranges from 5 to 12V. DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC. Over voltage protection. If the output voltage reaches the 17% above the programmed voltage this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage. If not used, it may be left floating. Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external frequency is increased according to the equation: 4.94 10 f S = 200kHz + ------------------------R T ( k ) Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 4.306 10 f S = 200kHz - ---------------------------RT ( k ) If the pin is not connected, the switching frequency is 200KHz. The voltage at this pin is fixed at 1.23V (typ). Forcing a 50A current into this pin, the built in oscillator stops to switch.
7 6
3
SS/INH
4-8
VID0 - 4
9 10 11 12
COMP FB GND PGOOD
13 14 15 16 17 18 19
PHASE UGATE BOOT PGND LGATE VCC OVP
20
RT
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ELECTRICAL CHARACTERISTCS (VCC = 12V, Tamb = 25C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit VCC SUPPLY CURRENT Icc Vcc Supply current Turn-On Vcc threshold Turn-Off Vcc threshold Rising VOCSET threshold ISS Soft start Current UGATE and LGATE open VOCSET=4.5V VOCSET=4.5V 3.6 1.24 10 5 4.6 mA V V V A 220 15 1.9 KHz % Vp-p POWER-ON
OSCILLATOR Free running frequency Total Variation Vosc Ramp amplitude RT = OPEN 6 K < RT to GND < 200 K RT = OPEN VID0, VID1, VID2, VID3, VID4 see Table1; Tamb = 0 to 70C -1 4 88 10 COMP=10pF 1 10 1.3 2 0.9 1.1 1.5 120 117 170 60 200 120 230 3 4 180 -15 200
REFERENCE AND DAC DACOUT Voltage Accuracy VID Pull-Up voltage ERROR AMPLIFIER DC Gain GBWP SR Gain-Bandwidth Product Slew-Rate High Side Source Current High Side Sink Resistance Low Side Source Current Low Side Sink Resistance Output Driver Dead Time PROTECTIONS Over Voltage Trip (VSEN/DACOUT) IOCSET IOVP OCSET Current Source OVP Sourcing Current VSEN Rising VOCSET = 4.5V VSEN > OVP Trip, VOVP=0V VSEN Rising VSEN Falling Upper and Lower threshold IPGOOD = -5mA % A mA dB MHz V/S A A ns 1 % V
GATE DRIVERS IUGATE RUGATE ILGATE RLGATE VBOOT - VPHASE=12V, VUGATE - VPHASE= 6V VBOOT-VPHASE=12V, IUGATE = 300mA Vcc=12V, VLGATE = 6V Vcc=12V, ILGATE = 300mA PHASE connected to GND
POWER GOOD Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) Hysteresis (VSEN/DACOUT) VPGOOD PGOOD Voltage Low 110 86 112 88 2 0.5 114 90 % % % V
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Table 1. VID Settings
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (V) 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (V) Output Off 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Device Description The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N-Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc ranging from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.3V to 2.05V with 50mV binary steps and from 2.1V to 3.5V with 100mV binary steps, with a maximum tolerance of 1% over temperature and line voltage variations. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/sec slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device protects against overcurrent conditions entering in HICCUP mode. The device monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. The device is available in SO20 package. Oscillator The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50A (Fsw=200KHz) and may be varied using an external resistor (R T) connected between RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin. In particular connecting it to GND the frequency is increased (current is sunk from the pin), according to the following relationship: 4.94 10 f S = 200kH z + ------------------------R T ( k )
6
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according to the following relationships:
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4.306 10 f S = 200kH z + ---------------------------R T ( k ) 15 10 f S = 200kH z + -------------------R T ( k ) Switching frequency variations vs. RT are reported in Fig.1.
7
7
VCC = 12V
VCC = 5V
Note that forcing a 50A current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1.
1 0 00 0
1 00 0
R e s is ta n ce [kO h m ]
10 0
10
R T to G N D R T to V C C =1 2 V R T to V C C =5 V
10
100
1000
F re q u e n cy [kH z]
Digital to Analog Converter The built-in digital to analog converter allows the adjustment of the output voltage from 1.30V to 2.05V with 50mV binary steps and from 2.10V to 3.50V with 100mV binary steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision of 1%. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5A current generator); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the overvoltage protection (OVP) thresholds. The VID code "11111" disable the device (as a short on the SS pin) and no output voltage is regulated. Soft Start and Inhibit At start-up a ramp is generated charging the external capacitor CSS by means of a 10A constant current, as shown in figure 1. When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to dis-
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charge the output capacitor. As V SS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly increases, as shown in figure 2. In this phase the system works in open loop. When V SS is equal to VCOMP the clamp on the output of the error amplifier is released. In any case another clamp on the input of the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see figure 2). In this second phase the system works in closed loop with a growing reference. As the output voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss increases until a maximum value of about 4V. The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept off. Figure 2. Soft Start
V cc Turn-on threshold V cc Vin V in Turn-on threshold V ss
to G ND
1V 0.5V
LGATE
Vout
Timing Diagram
Aquisition: CH1 = PHASE; CH2 = V OUT; CH3 = PGOOD; CH4 = VSS
Driver Section The driver capability on the high and low side drivers allows using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition. The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin. Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the low side turn-off. The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 4nF capacitive load has been used in these measurements. For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V. Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ VbootVphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
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Figure 3. High Side driver peak current. Vboot-Vphase=12V (left) Vboot-Vphase=5V (right)
CH1 = High Side Gate
CH4 = Gate Current
Figure 4. Low Side driver peak current. Vcc=12V (left) Vcc=5V (right)
CH1 = Low Side Gate
CH4 = Gate Current
Monitoring and Protections The output voltage is monitored by means of pin 1 (VSEN). If it is not within 12% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) grater than the nominal one. If the output voltage exceeds this threshold, the OVP pin is forced high, triggering an external SCR to shuts the supply (VIN) down, and also the lower driver is turned on as long as the over-voltage is detected. To perform the overcurrent protection the device compares the drop across the high side MOS, due to the RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (I P) can be calculated with the following relationship: I OCS R OCS I P = -------------------------------R DSON Where the typical value of IOCS is 200A. To calculate the ROCS value it must be considered the maximum RDSON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of
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overcurrent protection this relationship must be satisfied: l I P I OUT MAX + ---- = I PEA K 2 Where I is the inductance ripple current and IOUTMAX is the maximum output current. In case of output short circuit the soft start capacitor is discharged with constant current (10A typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode, as shown in figure 5a. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on. Figure 5.
9 8
L=1.5H, Vin=12V L=2H, Vin=12V L=3H, Vin=12V L=1.5H, Vin=5V L=2H, Vin=5V L=3H, Vin=5V
Inductor Ripple [A]
7 6 5 4 3 2 1 0 0.5 1.5 2.5
3.5
Output Voltage [V ]
a: Hiccup Mode
b: Inductor Ripple Current vs. Vout
Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN - V OUT V OUT L = ----------------------------- -------------V IN f S I L Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 5b shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response:
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L I t a pplic atio n = ----------------------------V IN - V OUT
L I t rem ov al = -------------V OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. Output Capacitor Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the range of tenth A/sec, the output capacitor is a basic component for the fast response of the power supply. In fact for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): VOUT = IOUT * ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: I OUT L V OUT = --------------------------------------------------------------------------------------------2 C OUT ( V INM IN D M AX - V OUT ) Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. Input Capacitor The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is: I rm s = I OUT D ( 1 - D ) Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are: P = ESR I rm s Compensation network design The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM module, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: at light load the output voltage will be higher than the nominal level, while at high load the output voltage will be lower than the nominal value.
2 2
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Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP ESR DROP
VMAX VDROOP
VNOM
VMIN
(a)
(b)
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) proportional to the output current. Since a sense resistor is not present, the output DC current is measured by using the intrinsic resistance of the inductance (a few m). So the low-pass filtered inductor voltage (that is the inductor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the schematic in figure 7, the static characteristic of the closed loop system is: R3 + R 8 // R9 R L R8 // R9 V OUT = V PRO G + V PRO G ------------------------------------- - ---------------------------------- I OUT R8 R2 Where VPROG is the output voltage of the digital to analog converter (i.e. the set point) and R L is the inductance resistance. The second term of the equation allows a positive offset at zero load (V+); the third term introduces the droop effect (VDROOP). Note that the droop effect is equal the ESR drop if: R L R 8 // R9 ---------------------------------- = ESR R8 Figure 7. Compensation network
V
IN
V
COMP
V
PHASE
L2
R
L
V
O UT
PW M
ESR R8
C18
Z
F
C 6-15 C 20 R4 R9
R3
C 25
V
PROG
ZI
R2
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired droop effect as follow: s Choose a value for R2 in the range of hundreds of K to obtain realistic values for the other components.
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s
From the above equations, it results:
+ V R 2 R L I M AX R8 = ----------------------- -------------------------- ; V PRO G V DROOP
V DROOP 1 R9 = R8 -------------------------- ------------------------------------ ; V DROOP R L I M AX 1 + -------------------------R L I M AX Where IMAX is the maximum output current. The component R3 must be chosen in order to obtain R3<s
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output impedance is equal to a resistance ROUT. It is easy to verify that the output voltage deviation under load transient is minimum when the output impedance is constant with frequency. To choose the other components of the compensation network, the transfer function of the voltage loop is considered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9). Figure 8. Compensation network definition
|A v |
2
fLC |R |
fC E
fEC
fC C
f
R0
fD |G lo o p | G0
f2
f1
f3
f
fc f
ConverterS ingularity
fLC = 1 / 2
LC
doublepole ESRzero Introduced by CeramicCapacitor
Compensati onNetworkS ingularity
fCE = 1 / 2 ESR C OUT = 1 / 2 ESR Cceramic f EC = 1 / 2 Rceramic Cceramic f CC
f1 = 1 / 2 R 4 C 20 f2 = 1 / 2 ( R 3 + R 4 ) C 20 f3 = 1 / 2 R 3 C 25 fd = 1 / 2 Rd C 25
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later, this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this assumption, the voltage loop has the following transfer function:
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ZC ( s ) Zf ( s ) Vin G loo p ( s ) = Av ( s ) R ( s ) = Av ( s ) ------------- Where Av ( s ) = --------------- -----------------------------------V o sc Z C ( s ) + Z L ( s ) Zi ( s ) Where ZC(s) and ZL(s) are the output capacitor and inductor impedance respectively. The expression of ZI(s) may be simplified as follow: 2 R3 1 1 Rd 1 + s ( 1 + d ) + s ------- 1 d Rd -- C 25 R4 + -- C20 R 3 Rd s s Z I ( s ) = --------------------------------- + ----------------------------------------------------- = -------------------------------------------------------------------------------------------------- = (1 + s 2 ) (1 + s d ) 1 Rd + -- C25 R 4 + 1 C20 + R3 -s s 1 + s R3 ( 1 + s ) ------- d 1 Rd = R d -------------------------------------------------------------------( 1 + s 2) ( 1 + s d ) Where: 1 = R4xC20, 2 = (R4+R3)xC20 and d = RdxC25. The regulator transfer function became now: ( 1 + s 2 ) ( 1 + s d ) R ( s ) ------------------------------------------------------------------------------------------------------R3 s C 18 R d 1 + s ------- d ( 1 + s 1 ) Rd Figure 8 shows a method to select the regulator components (please note that the frequencies f EC and fCC corresponds to the singularities introduced by additional ceramic capacitors in parallel to the output main electrolytic capacitor). s To obtain a flat frequency response of the output impedance, the droop time constant d has to be equal to the inductor time constant (see the note at the end of the section): L d = R d C 25 = ------ = L RL
s
L C25 = ----------------------( R L Rd )
To obtain a constant -20dB/dec Gloop(s) shape the singularity f1 and f2 are placed in proximity of fCE and fLC respectively. This implies that: f LC f2 --- = -------f CE f1 f1 = f CE f LC R4 = R3 -------- - 1 f CE C20 1 = -- R 4 f CE 2
s
To obtain a Gloop bandwidth of fC, results:
G0 f LC = 1 fC fC V IN C20 // C25 G 0 = A 0 R 0 = ----------------- ---------------------------- = ------C18 Vosc fLC C20 C25 f LC VIN C 18 = ----------------- ---------------------------- ------Vosc C20 + C25 f C
Note. To understand the reason of the previous assumption, the scheme in figure 9 must be considered. In this scheme, the inductor current has been substituted by the load current, because in the frequencies range of interest for the Droop function these current are substantially the same and it was supposed that the droop network don't represent a charge for the inductor.
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Figure 9. Voltage regulation with droop function block scheme
V com p
A v(s)
V out
R (s )
It results:
R OUT
1 + s L 1 + s d
Iout
1 + s L 1 + sL G LO O P Vo Z OUT = --------------- = R d ----------------- ---------------------------- = R OUT -----------------I LO AD 1 + s d 1 + G L O O P 1 + sd
Because in the interested range |Gloop|>>1. To obtain a flat shape, the relationship considered will naturally follow. Demo Board Description The L6911C demo board shows the operation of the device in a standard VRM 8.4 application. This evaluation board allows voltage adjustability (1.3V - 3.5V) through the switches S1-S5 and high output current capability (up to 14A). The device is supplied by the 12V input rail while the power conversion starts from the 5V input rail. The device is also able to operate with a 5V supply voltage; in this case 12V input can be directly connected to the 5V power source. The four layers demo board's copper thickness is of 70m in order to minimize conduction losses considering the high current that the circuit is able to deliver. Figure 10 shows the demo board's schematic circuit. Figure 10. Demo Board Schematic
F1 +5 VIN L1
C21-22 GNDIN G1 Q8 C1-5
BOOT
D1
VCC
OVP
C24 19 2
UGATE OCSET
C23 R7 R13 Q1-2 L2 VOUTCORE
15 18
+12Vcc C17 GND12 S1 S2 S3 S4 S5
GND
11
VID0
14
PHASE
4
VID1
5
VID2
13
6
VID3
7
VID4
U1 17 L6911C16
12 1 9 10 C18 C19
VFB
LGATE
R14 Q4-5 D2 C6-15 R12 GNDCORE
PGND
8
SS
PGOOD
3
OSC
PWRGD
VSEN
20 C16 R1
R8 R3 C20 R4 R9 C25
COMP
R5
R2
L6911-L6912 EVALUATION KIT REV.
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Efficiency Figure 11 shows the measured efficiency versus load current for different values of output voltage. The measure was done at Vin=5V for different values of the output voltage (2.05V and 2.75V). Two different measurements were done using IC supply voltage of 5V and 12V. In the application two mosfets STS12NF30L (30V, 10m typ @ Vgs=4.5V) connected in parallel are used for both the low and the high side. The board has been layed out with the possibility to use up to three SO8 mosfets for both high and low side switch. Two D2PACK mosfets (one for each high and low side) may also be used in order to allow the maximum flexibility in meeting different requirements. Figure 11. Efficiency vs. load
95 90 95 90
Efficiency [%]
80 75 70 65 60 55 0 2 4 6 8 10 12 14 16
Efficiency [%]
85
85 80 75 70 65 60 55 0 2 4 6 8 10 12 14 16
Vout = 1.7V Vout = 2.0V Vout = 2.5V
Vout = 1.7V Vout = 2.0V Vout = 2.5V
Out put Current [A]
Out put C ur r en t [ A ]
Vcc = 12V; Vin = 5V
Vcc = Vin = 5V
Figure 13. Load Transient Response Details Load Transient Response Figure 12 shows the demo board response to a load transient application. The load transient applied changes from 0A to 14A on the output current (Channel 4). It may be observed that output voltage (Channel 1) remains within the 100mV tolerance across the regulated voltage. Figure 13 shows details about the the circuit response during current rising and falling edge; it is possible to observe that the duty cycle of the Phase signal (Channel 2) goes up to 100% or down to 0% if necessary. Figure 12. Load Transient Response
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Inductor selection Since the maximum output current is equal to 14A, to have a 30% ripple (4A) in worst case a 3H inductor has been chosen. So the ripple is 4.1A @ 3.5V with VIN=12V and 1.7A @ 3.5V with VIN = 5V. In worst case the peak is equal to 18.1A. Output Capacitor In the demo ten Sanyo capacitors, model 6MV1000GX are used, with a maximum ESR equal to 69m. Therefore, the resultant ESR is 69m/10 = 1.9m. For a load transient of 14A in worst case the drop results: Vout = 14 * 0.00069 = 96.6mV The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cycle is equal to 100% results in 13mV with 2.5V of programmed output. Input Capacitor For IOUT = 14A and D = 0.5 (worst case for input ripple current), Irms is equal to 7A. Five Sanyo electrolytic capacitors 25MV330GX, with a maximum ESR equal to 69m, are chosen to sustain the ripple. Therefore, the resultant ESR is equal to 69m/5 = 13.8m. So the losses in worst case are: P = ESR I rm s = 670 mW Over-Current Protection Substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170A; IP = 19A; RDSONMAX = 9m) it results that ROCS = 1k. Part List
R2 R3, R7 R4 R5, R8 R9 R12 R13, R14 C1, C2...C5 C6, C7...C15 C16, C17, C24, C25 C18 C19 C20 C21, C22 C23 L1 L2 U1 Q1, Q2...Q6 D1 D2 F1 499k 1k 20 20k 15k 1K 0 330 1000 100n 2.2n 8.2n 82n 1 1n 1.5 3 L6911C STS12NF30L 1N4148 STPS3L25U 251015A-15 SANYO - 25MV330GX SANYO - 6MV1000GX Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic T44-52 Core, 7T-18AWG T50-52B Core, 10T-16AWG STMicroelectronics STMicroelectronics STMicroelectronics STMicroelectronics Littlefuse SO20 SO8 SOT23 SMB AXIAL 1% 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 Radial 8x20mm Radial 8x20mm SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 1206 SMD 0805
2
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PCB AND COMPONENTS LAYOUTS Figure 14. PCB and Components Layouts
Component Side
Internal Ground Plane
Figure 15. PCB and Components Layouts
Internal Layer
Solder Side
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Application Circuit Examples Figure 16 reports the schematic circuit for a motherboard chipset power supply. This application works from a single 5V power supply and is able to deliver up to 10A with a 300KHz switching frequency.
Figure 16. Motherboard chipset power supply; 2.5Vout, 10A
CoilCraft DO3316P 1uH 10A fuse +5 VIN GNDIN 1N4148 2x1uF 3x220uF ceram ic Sanyo
B OO T
O VP
1n 100n 19 2 14 13
O CS E T
15
VCC
18 11 4
1k
100nF
G ND
U GA TE
V ID0
STS12NF30L
P H AS E
CoilCraft DO5022P 1.5uH VOUTCORE 5x470uF Sanyo TPB GNDCORE PWRGD
V ID1
5 6 7 8 3 20 9
C OMP
V ID2
V ID3
U1 17 L6911C
16 12 1 10 220pF 680pF 100k
V FB
LG ATE
STS12NF30L
P GN D
STPS3L25U
10k
V ID4
P GO OD
SS
O SC
V S EN
100n
43k
10k 5.6n 220
750k
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mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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